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FEATURES
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LTM4612 Ultralow Noise 36VIN, 15VOUT, 5A, DC/DC Module DESCRIPTION
The LTM(R)4612 is a complete, ultralow noise, high voltage input and output, 5A switching mode DC/DC power supply. Included in the package are the switching controller, power FETs, inductor and all support components. Operating over an input voltage range of 5V to 36V, the LTM4612 supports an output voltage range of 3.3V to 15V, set by a single resistor. Only bulk input and output capacitors are needed to finish the design. High switching frequency and an adaptive on-time current mode architecture enables a very fast transient response to line and load changes without sacrificing stability. The onboard input filter and noise cancellation circuits achieve low noise coupling, thus effectively reducing the electromagnetic interference (EMI)--see Figures 4 and 8. Furthermore, the DC/DC ModuleTM can be synchronized with an external clock for reducing undesirable frequency harmonics and allows PolyPhase(R) operation for high load currents. The LTM4612 is offered in a space saving and thermally enhanced 15mm x 15mm x 2.8mm LGA package, which enables utilization of unused space on the bottom of PC boards for high density point-of-load regulation. The LTM4612 is Pb-free and RoHS compliant.
, LT, LTC, LTM and PolyPhase are registered trademarks of Linear Technology Corporation. Module is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners.
Complete Low EMI Switch Mode Power Supply CISPR 22 Class B Compliant Wide Input Voltage Range: 5V to 36V 5A DC, 7A Peak Output Current 3.3V to 15V Output Voltage Range Low Input and Output Referred Noise Output Voltage Tracking and Margining PLL Frequency Synchronization 1.5% Set Point Accuracy Power Good Tracks with Margining Current Foldback Protection (Disabled at Start-Up) Parallel/Current Sharing Ultrafast Transient Response Current Mode Control Programmable Soft-Start Output Overvoltage Protection -55C to 125C Operating Temperature Range (LTM4612MPV) Small Surface Mount Footprint, Low Profile (15mm x 15mm x 2.8mm) LGA Package
APPLICATIONS
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Telecom and Networking Equipment Industrial and Avionic Equipment RF Systems
TYPICAL APPLICATION
12V/5A Ultralow Noise Module with 22V to 36V Input
VIN 22V TO 36V CLOCK SYNC 2M 100k VIN PLLIN VOUT PGOOD RUN LTM4612 COMP INTVCC DRVCC fSET TRACK/SS VD 10F SGND VFB 5.23k FCB MARG0 MARG1 MPGM PGND MARGIN CONTROL 392k 5% MARGIN
4612 TA01
Efficiency vs Load Current at 12V Output
100 95 90 EFFICIENCY (%) VOUT 12V 5A COUT 85 80 75 70 65 60 55 50 0 1 24VIN 12VOUT 28VIN 12VOUT 36VIN 12VOUT 2 3 4 OUTPUT CURRENT (A) 5
4612 TA01b
100pF
CIN
0.01F
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LTM4612 ABSOLUTE MAXIMUM RATINGS
(Note 1)
PIN CONFIGURATION
INTVCC PLLIN TRACK/SS RUN COMP MPGM VD SGND fSET MARG0 MARG1 DRVCC VFB PGOOD SGND NC NC NC FCB TOP VIEW
INTVCC, DRVCC ............................................. -0.3V to 6V VOUT ........................................................... -0.3V to 16V PLLIN, FCB, TRACK/SS, MPGM, MARG0, MARG1, PGOOD, fSET ...........-0.3V to INTVCC + 0.3V RUN ............................................................. -0.3V to 5V VFB, COMP ................................................ -0.3V to 2.7V VIN , VD ....................................................... -0.3V to 36V Internal Operating Temperature Range (Note 2) E and I Grades ...................................-40C to 125C MP Grade...........................................-55C to 125C Junction Temperature ........................................... 125C Storage Temperature Range...................-55C to 125C
A VIN B BANK 1 C D E PGND BANK 2 F G H J VOUT K BANK 3 L M
1 2 3 4 5 6 7 8 9 10 11 12 LGA PACKAGE 133-LEAD (15mm x 15mm x 2.8mm) TJMAX = 125C, JA = 15C/W, JC = 6C/W JA DERIVED FROM 95mm x 76mm PCB WITH 4 LAYERS WEIGHT = 1.7g
ORDER INFORMATION
LEAD FREE FINISH LTM4612EV#PBF LTM4612IV#PBF LTM4612MPV#PBF TRAY LTM4612EV#PBF LTM4612IV#PBF LTM4612MPV#PBF PART MARKING* LTM4612V LTM4612V LTM4612MPV PACKAGE DESCRIPTION 133-Lead (15mm x 15mm x 2.8mm) LGA 133-Lead (15mm x 15mm x 2.8mm) LGA 133-Lead (15mm x 15mm x 2.8mm) LGA TEMPERATURE RANGE -40C to 125C -40C to 125C -55C to 125C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ This product is only offered in trays. For more information go to: http://www.linear.com/packaging/
ELECTRICAL CHARACTERISTICS
SYMBOL VIN(DC) VOUT(DC) PARAMETER Input DC Voltage Output Voltage
The l denotes the specifications which apply over the full internal operating temperature range, otherwise specifications are at TA = 25C, VIN = 24V, unless otherwise noted. Per Typical Application (front page) configuration.
CONDITIONS
l
MIN 5 11.89 11.89
TYP
MAX 36
UNITS V V V V
CIN = 10F x 3, COUT = 300F; FCB = 0 VIN = 24V, VOUT = 12V, IOUT = 0A VIN = 36V, VOUT=12V, IOUT = 0A IOUT = 0A IOUT = 0A; CIN = 10F x 2, COUT = 200F; VOUT = 12V VIN = 24V VIN = 36V
l l
12.07 12.07 3.2
12.25 12.25 4.8
Input Specifications VIN(UVLO) IINRUSH(VIN) Undervoltage Lockout Threshold Input Inrush Current at Start-Up
0.6 0.7
A A
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LTM4612 ELECTRICAL CHARACTERISTICS
SYMBOL IQ(VIN) PARAMETER Input Supply Bias Current
The l denotes the specifications which apply over the full internal operating temperature range, otherwise specifications are at TA = 25C, VIN = 24V, unless otherwise noted. Per Typical Application (front page) configuration.
CONDITIONS VIN = 36V, No Switching VIN = 36V, VOUT = 12V, Switching Continuous VIN = 24V, No Switching VIN = 24V, VOUT = 12V, Switching Continuous Shutdown, RUN = 0, VIN = 36V VIN = 36V, VOUT = 12V, IOUT = 5A VIN = 24V, VOUT = 12V, IOUT = 5A VIN = 36V, RUN > 2V, IOUT = 0A VIN = 24V, VOUT = 12V (Note 4) VOUT = 12V, FCB = 0V, VIN = 22V to 36V, IOUT = 0A VOUT = 12V, FCB = 0V, IOUT = 0A to 5A (Note 4) VIN = 36V VIN = 24V IOUT = 0A, CIN = 2 x 10F X5R Ceramic and 1 x 100F Electrolytic, 1 x 10F X5R Ceramic on VD Pins VIN = 24V, VOUT = 5V VIN = 24V, VOUT = 12V IOUT = 0A, COUT = 2 x 22F 2 x 47F X5R Ceramic , VIN = 24V, VOUT = 5V VIN = 24V, VOUT = 12V IOUT = 1A, VIN = 24V, VOUT = 12V COUT = 200F VOUT = 12V, IOUT = 0A , VIN = 36V VIN = 24V COUT = 300F VOUT = 12V, IOUT = 1A , Resistive Load VIN = 36V VIN = 24V Load: 0% to 50% to 0% of Full Load COUT = 2 x 22F Ceramic, 150F Bulk VIN = 24V, VOUT = 12V COUT = 200F VIN = 36V, VOUT = 12V VIN = 24V, VOUT = 12V IOUT = 0A, VOUT = 12V VSS/TRACK = 0V VFCB = 0V (Note 3) (Note 3)
l l l l
MIN
TYP 4.5 57 3.5 48 50 1.85 2.72
MAX
UNITS mA mA mA mA A A A
IS(VIN) VINTVCC IOUT(DC) VOUT(LINE) VOUT VOUT(LOAD) VOUT VIN(AC)
Input Supply Current Internal VCC Voltage Output Continuous Current Range Line Regulation Accuracy Load Regulation Accuracy
4.7 0
5
5.3 5
V A % % %
Output Specifications
0.05 0.3 0.3
0.3 0.6 0.6
Input Ripple Voltage
7.2 3.4
mVP-P mVP-P
VOUT(AC)
Output Ripple Voltage
17.5 12.5 940 20 20
mVP-P mVP-P kHz mV mV
fS VOUT(START)
Output Ripple Voltage Frequency Turn-On Overshoot, TRACK/SS = 10nF Turn-On Time, TRACK/SS = Open
tSTART
0.5 0.5 153 37 9 9 0.594 1 -1 0.57 0.6 1.5 -1.5 0.6 -1 50 250 0.606 1.9 -2 0.63 -2 100 400
ms ms mV s A A V V A V A ns ns
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VOUT(LS)
Peak Deviation for Dynamic Load
tSETTLE IOUT(PK)
Settling Time for Dynamic Load Step Load: 0% to 50% to 0% of Full Load, VIN = 24V Output Current Limit
Control Section VFB VRUN ISS / TRACK VFCB IFCB tON(MIN) tOFF(MIN) Voltage at VFB Pin RUN Pin On/Off Threshold Soft-Start Charging Current Forced Continuous Threshold Forced Continuous Pin Current Minimum On-Time Minimum Off-Time
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LTM4612 ELECTRICAL CHARACTERISTICS
SYMBOL RPLLIN IDRVCC RFBHI VMPGM VMARG0, VMARG1 PGOOD VFBH VFBL VFB(HYS) VPGL PGOOD Upper Threshold PGOOD Lower Threshold PGOOD Hysteresis PGOOD Low Voltage VFB Rising VFB Falling VFB Returning IPGOOD = 5mA 7 -7 10 -10 1.5 0.15 0.4 13 -13 % % % V PARAMETER PLLIN Input Resistor Current into DRVCC Pin Resistor Between VOUT and VFB Pins Margin Reference Voltage MARG0, MARG1 Voltage Thresholds VOUT = 12V, IOUT = 1A 99.5
The l denotes the specifications which apply over the -40C to 85C operating temperature range, otherwise specifications are at TA = 25C, VIN = 24V, unless otherwise noted. Per Typical Application (front page) configuration.
CONDITIONS MIN TYP 50 22 100 1.18 1.4 30 100.5 MAX UNITS k mA k V V
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LTM4612E is guaranteed to meet performance specifications over the 0C to 125C internal operating temperature range. Specifications over the -40C to 125C internal operating temperature range are assured by design, characterization and correlation with statistical process controls. The LTM4612I is guaranteed to meet specifications over the
-40C to 125C internal operating temperature range. The LTM4612MP is guaranteed and tested over the full -55C to 125C internal operating temperature range. Note that the maximum ambient temperature is determined by specific operating conditions in conjunction with board layout, the rated package thermal resistance and other environmental factors. Note 3: 100% tested at die level only. Note 4: See the Output Current Derating curves for different VIN, VOUT and TA.
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LTM4612 TYPICAL PERFORMANCE CHARACTERISTICS (Refer to Figure 18)
Efficiency vs Load Current with 3.3VOUT (FCB = 0)
100 95 90 EFFICIENCY (%) EFFICIENCY (%) 85 80 75 70 65 60 55 50 0 1 5VIN 3.3VOUT 12VIN 3.3VOUT 24VIN 3.3VOUT 36VIN 3.3VOUT 2 3 LOAD CURRENT (A) 4 5
4612 G01
Efficiency vs Load Current with 5VOUT (FCB = 0)
95 90 85 EFFICIENCY (%) 80 75 70 65 60 55 50 0 1 12VIN 5VOUT 24VIN 5VOUT 36VIN 5VOUT 2 3 LOAD CURRENT (A) 4 5
4612 G02
Efficiency vs Load Current with 12VOUT (FCB = 0)
100 95 90 85 80 75 70 65 60 55 50 0 1 20VIN 12VOUT 24VIN 12VOUT 28VIN 12VOUT 36VIN 12VOUT 2 3 LOAD CURRENT (A) 4 5
4612 G03
Efficiency vs Load Current with 15VOUT (FCB = 0, Refer to Figure 20)
100 95 90 EFFICIENCY (%) 85 80 75 70 65 60 0 1 28VIN 15VOUT 32VIN 15VOUT 36VIN 15VOUT 2 3 LOAD CURRENT (A) 4 5
4612 G04
Transient Response from 12VIN to 3.3VOUT
Transient Response from 12VIN to 5VOUT
2A/DIV
2A/DIV
100mV/DIV
100mV/DIV
50s/DIV
4612 G05
50s/DIV
4612 G06
LOAD STEP: 0A to 3A COUT = 2 22F CERAMIC CAPACITORS AND 2 47F CERAMIC CAPACITORS
LOAD STEP: 0A to 3A COUT = 2 22F CERAMIC CAPACITORS AND 2 47F CERAMIC CAPACITORS
Transient Response from 24VIN to 12VOUT
Start-Up with 24VIN to 12VOUT at IOUT = 0A
Start-Up with 24VIN to 12VOUT at IOUT = 5A
2A/DIV
IIN 0.2A/DIV IIN 1A/DIV
200mV/ DIV VOUT 5V/DIV 50s/DIV
4612 G07
VOUT 5V/DIV 500s/DIV
4612 G08
500s/DIV
4612 G09
LOAD STEP: 0A to 3A COUT = 2 22F CERAMIC CAPACITORS AND 2 47F CERAMIC CAPACITORS
SOFT-START CAPACITOR: 3.9nF CIN = 3 10F CERAMIC CAPACITORS AND 1 47F OSCON CAPACITOR
SOFT-START CAPACITOR: 3.9nF CIN = 3 10F CERAMIC CAPACITORS AND 1 47F OSCON CAPACITOR
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LTM4612 TYPICAL PERFORMANCE CHARACTERISTICS
Start-Up with 24VIN to 12VOUT at IOUT = 5A, TA = -55C Short-Circuit with 24VIN to 12VOUT at IOUT = 0A Short-Circuit with 24VIN to 12VOUT at IOUT = 5A
IIN 2A/DIV VOUT 5V/DIV IIN 0.2A/DIV VOUT 5V/DIV VOUT 5V/DIV
IIN 1A/DIV 500s/DIV
4612 G10
50s/DIV
4612 G11
20s/DIV
4612 G12
SOFT-START CAPACITOR: 3.9nF CIN = 3 10F CERAMIC CAPACITORS AND 1 47F OSCON CAPACITOR
COUT = 2 22F CERAMIC CAPACITORS AND 2 47F CERAMIC CAPACITORS
COUT = 2 22F CERAMIC CAPACITORS AND 2 47F CERAMIC CAPACITORS
VIN to VOUT Step-Down Ratio
36 30 24 VIN (V) 18 12 6 0 3.3 4 OPERATING REGION WITH DEFAULT FREQUENCY 50mV/DIV SEE FREQUENCY ADJUSTMENT SECTION FOR OPERATIONS OUTSIDE THIS REGION
Input Ripple
Output Ripple
10mV/DIV
6
10 8 VOUT (V)
12
14 15
4612 G13
1s/DIV
4612 G14
1s/DIV VIN = 24V VOUT = 12V AT 5A RESISTIVE LOAD COUT = 2 22F 16V CERAMIC AND 2 47F 16V CERAMIC
4612 G15
VIN = 24V VOUT = 12V AT 5A RESISTIVE LOAD CIN = 3 10F 50V CERAMIC 1 100F BULK
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LTM4612 PIN FUNCTIONS
(See Package Description for Pin Assignments)
VIN (Bank 1): Power Input Pins. Apply input voltage between these pins and PGND pins. Recommend placing input decoupling capacitance directly between VIN pins and PGND pins. PGND (Bank 2): Power Ground Pins for Both Input and Output Returns. VOUT (Bank 3): Power Output Pins. Apply output load between these pins and PGND pins. Recommend placing output decoupling capacitance directly between these pins and GND pins (see the LTM4612 Pin Configuration below). VD (Pins B7, C7): Top FET Drain Pins. Add more capacitors between VD and ground to handle the input RMS current and reduce the input ripple further. DRVCC (Pins C10, E11, E12): These pins normally connect to INTVCC for powering the internal MOSFET drivers. They can be biased up to 6V from an external supply with about 50mA capability. This improves efficiency at the higher input voltages by reducing power dissipation in the module. INTVCC (Pin A7): This pin is for additional decoupling of the 5V internal regulator. PLLIN (Pin A8): External Clock Synchronization Input to the Phase Detector. This pin is internally terminated to SGND with a 50k resistor. Apply a clock above 2V and below INTVCC. See the Applications Information section. FCB (Pin M12): Forced Continuous Input. Connect this pin to SGND to force continuous synchronization operation at
INTVCC PLLIN TRACK/SS RUN COMP MPGM TOP VIEW
low load, to INTVCC to enable discontinuous mode operation at low load or to a resistive divider from a secondary output when using a secondary winding. TRACK/SS (Pin A9): Output Voltage Tracking and Soft-Start Pin. When the module is configured as a master output, then a soft-start capacitor is placed on this pin to ground to control the master ramp rate. A soft-start capacitor can be used for soft-start turn-on as a standalone regulator. Slave operation is performed by putting a resistor divider from the master output to the ground, and connecting the center point of the divider to this pin. See the Applications Information section. MPGM (Pins A12, B11): Programmable Margining Input. A resistor from these pins to ground sets a current that is equal to 1.18V/R. This current multiplied by 10k will equal a value in millivolts that is a percentage of the 0.6V reference voltage. See the Applications Information section. To parallel LTM4612s, each requires an individual MPGM resistor. Do not tie MPGM pins together. fSET (Pin B12): Frequency Set Internally to 850kHz at 12V Output. An external resistor can be placed from this pin to ground to increase frequency. This pin can be decoupled with a 1000pF capacitor. See the Applications Information section for frequency adjustment. VFB (Pin F12): The Negative Input of the Error Amplifier. Internally, this pin is connected to VOUT with a 100k precision resistor. Different output voltages can be programmed with an additional resistor between the VFB and SGND pins. See the Applications Information section. MARG0 (Pin C12): LSB Logic Input for the Margining Function. Together with the MARG1 pin, the MARG0 pin will determine if a margin high, margin low, or no margin state is applied. The pin has an internal pull-down resistor of 50k. See the Applications Information section. MARG1 (Pins C11, D12): MSB Logic Input for the Margining Function. Together with the MARG0 pin, the MARG1 pin will determine if a margin high, margin low, or no margin state is applied. The pins have an internal pull-down resistor of 50k. See the Applications Information section. SGND (Pins D9, H12): Signal Ground Pins. These pins connect to PGND at output capacitor point.
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A VIN B BANK 1 C D E PGND BANK 2 F G H J VOUT K BANK 3 L M
VD SGND
fSET MARG0 MARG1 DRVCC VFB PGOOD SGND NC NC NC FCB
1 2 3 4 5 6 7 8 9 10 11 12 LGA PACKAGE 133-LEAD (15mm x 15mm x 2.8mm)
LTM4612 Pin Configuration
7
LTM4612 PIN FUNCTIONS
COMP (Pins A11, D11): Current Control Threshold and Error Amplifier Compensation Point. The current comparator threshold increases with this control voltage. The voltage ranges from 0V to 2.4V with 0.7V corresponding to zero sense voltage (zero current). PGOOD (Pin G12): Output Voltage Power Good Indicator. Open-drain logic output that is pulled to ground when the output voltage is not within 10% of the regulation point, after a 25s power bad mask timer expires. RUN (Pins A10, B9): Run Control Pins. A voltage above 1.9V will turn on the module, and below 1V will turn off the module. A programmable UVLO function can be accomplished with a resistor from VIN to this pin that is has a 5.1V zener to ground. Maximum pin voltage is 5V. NC (Pins J12, K12, L12): No Connect Pins.
BLOCK DIAGRAM
> 1.9V = ON < 1V = OFF MAX = 5V VOUT RUN PGOOD COMP 100k VD INTERNAL COMP SGND MARG1 MARG0 VFB RFB 5.23k fSET 93.1k PGND FCB 10k MPGM TRACK/SS CSS PLLIN 4.7F INTVCC
4612 F01
5.1V ZENER
1F
INPUT FILTER
+
VIN 20V TO 36V CIN
CD POWER CONTROL M1 VOUT 12V AT 4A 50k 50k M2 NOISE CANCELLATION 10F
+
COUT
50k
DRVCC
Figure 1. Simplified Block Diagram
DECOUPLING REQUIREMENTS
SYMBOL CIN COUT PARAMETER External Input Capacitor Requirement (VIN = 20V to 36V, VOUT = 12V) External Output Capacitor Requirement (VIN = 20V to 36V, VOUT = 12V)
Specifications are at TA = 25C. Use Figure 1 configuration.
MIN 10 100 150 TYP MAX UNITS F F
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CONDITIONS IOUT = 4A IOUT = 4A
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LTM4612 OPERATION
Power Module Description The LTM4612 is a standalone nonisolated switching mode DC/DC power supply. It can deliver 5A of DC output current with some external input and output capacitors. This module provides precisely regulated output voltage programmable via one external resistor from 3.3VDC to 15VDC over a 5V to 36V wide input voltage. The typical application schematic is shown in Figure 18. The LTM4612 has an integrated constant on-time current mode regulator, ultralow RDS(ON) FETs with fast switching speed and integrated Schottky diodes. The typical switching frequency is 850kHz at full load. With current mode control and internal feedback loop compensation, the LTM4612 module has sufficient stability margins and good transient performance under a wide range of operating conditions and with a wide range of output capacitors, even all ceramic output capacitors. Current mode control provides cycle-by-cycle fast current limiting. Moreover, foldback current limiting is provided in an overcurrent condition while VFB drops. Internal overvoltage and undervoltage comparators pull the opendrain PGOOD output low if the output feedback voltage exits a 10% window around the regulation point. Furthermore, in an overvoltage condition, internal top FET M1 is turned off and bottom FET M2 is turned on and held on until the overvoltage condition clears. Input filter and noise cancellation circuitry reduce the noise coupling to I/O sides, and ensure the electromagnetic interference (EMI) meets the limits of CISPR 22 and CISPR 25. Pulling the RUN pin below 1V forces the controller into its shutdown state, turning off both M1 and M2. At low load currents, discontinuous mode (DCM) operation can be enabled to achieve higher efficiency compared to continuous mode (CCM) by setting FCB pin higher than 0.6V. When the DRVCC pin is connected to INTVCC, an integrated 5V linear regulator powers the internal gate drivers. If a 5V external bias supply is applied on DRVCC pin, then an efficiency improvement will occur due to the reduced power loss in the internal linear regulator. This is especially true at the higher input voltage range. The MPGM, MARG0, and MARG1 pins are used to support voltage margining, where the percentage of margin is programmed by the MPGM pin, and the MARG0 and MARG1 selected margining. The PLLIN pin provides frequency synchronization of the device to an external clock. The TRACK/SS pin is used for power supply tracking and soft-start programming.
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LTM4612 APPLICATIONS INFORMATION
The typical LTM4612 application circuit is shown in Figure 18. External component selection is primarily determined by the maximum load current and output voltage. Refer to Table 2 for specific external capacitor requirements for a particular application. VIN to VOUT Stepdown Ratios There are restrictions in the maximum VIN and VOUT step down ratio that can be achieved for a given input voltage. These constraints are shown in the Typical Performance Characteristic curve labeled "VIN to VOUT Step-Down Ratio." Note that additional thermal derating may be applied. See the Thermal Considerations and Output Current Derating section in this data sheet. Output Voltage Programming and Margining The PWM controller has an internal 0.6V reference voltage. As shown in the Block Diagram, a 100k internal feedback resistor connects the VOUT and VFB pins together. Adding a resistor, RFB, from the VFB pin to the SGND pin programs the output voltage. 100k + RFB VOUT = 0.6 V * RFB
Table 1. RFB Standard 1% Resistor Values vs VOUT
VOUT (V) RFB (k) 3.3 22.1 5 13.7 6 11 8 8.06 10 6.34 12 5.23 14 4.42 15 4.12
200 2 4 6 10 8 VOUT (V) 12 14 16
4612 F02
The output margining will be margining of the value. This is controlled by the MARG0 and MARG1 pins. See the truth table below:
MARG1 LOW LOW HIGH HIGH MARG0 LOW HIGH LOW HIGH MODE NO MARGIN MARGIN UP MARGIN DOWN NO MARGIN
Operating Frequency The operating frequency of the LTM4612 is optimized to achieve the compact package size and the minimum output ripple voltage while still keeping high efficiency. As shown in Figure 2, the frequency is linearly increased with larger output voltages to keep the low output current ripple. Figure 3 shows the inductor current ripple I with different output voltages. In most applications, no additional frequency adjusting is required.
1200
1000 FREQUENCY (kHz) INDUCTOR CURRENT RIPPLE I (A)
800
600
400
The MPGM pin programs a current that when multiplied by an internal 10k resistor sets up the 0.6V reference offset for margining. A 1.18V reference divided by the RPGM resistor on the MPGM pin programs the current. Calculate VOUT(MARGIN): VOUT(MARGIN) = %VOUT * VOUT 100
Figure 2. Operating Frequency vs Output Voltage
3.5 3.0 VIN = 36V 2.5 2.0 VIN = 20V 1.5 1.0 0.5 2 4 6 8 10 VOUT (V) 12 14 16
4612 F03
Where %VOUT is the percentage of VOUT to be margined, and VOUT(MARGIN) is the margin quantity in volts: V 1.18 V RPGM = OUT * * 10k 0.6 V VOUT(MARGIN) Where RPGM is the resistor value to place on the MPGM pin to ground.
VIN = 28V
Figure 3. Inductor Current Ripple vs Output Voltage
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LTM4612 APPLICATIONS INFORMATION
If lower output ripple is required, the operating frequency f can be increased by adding a resistor RfSET between fSET pin and SGND, as shown in Figure 19. f= 1 . 5 * 10 - 10 VOUT (R fSET || 93 . 1k ) In this equation, is the estimated efficiency of the power module. Note the capacitor ripple current ratings are often based on temperature and hours of life. This makes it advisable to properly derate the input capacitor, or choose a capacitor rated at a higher temperature than required. Always contact the capacitor manufacturer for derating requirements. In a typical 5A output application, one very low ESR, X5R or X7R, 10F ceramic capacitor is recommended for C1. This decoupling capacitor should be placed directly adjacent to the module VD pins in the PCB layout to minimize the trace inductance and high frequency AC noise. Each 10F ceramic is typically good for 2A to 3A of RMS ripple current. Refer to your ceramics capacitor catalog for the RMS current ratings. To attenuate the high frequency noise, extra input capacitors should be connected to the VIN pads and placed before the high frequency inductor to form the filter. One of these low ESR ceramic input capacitors is recommended to be close to the connection into the system board. A large bulk 100F capacitor is only needed if the input source impedance is compromised by long inductive leads or traces. Figure 4 shows the conducted EMI testing results to meet the Level 5 of the CISPR 25 limit. For different applications, input capacitance may be varied to meet different conducted EMI limits.
80 70 SIGNAL AMPLITUDE (dBV) 60 50 40 30 20 10 0 0.15 1 FREQUENCY (MHz) 10 30
4612 F04
For output voltages more than 12V, the frequency can be higher than 1MHz, thus reducing the efficiency significantly. Additionally, the minimum off time 400ns normally limits the operation when the input voltage is close to the output voltage. Therefore, it is recommended to lower the frequency in these conditions by connecting a resistor (RfSET) from the fSET pin to VIN, as shown in Figure 20. f= VOUT 3 * R fSET * 93 . 1k 5 * 10 - 11 R fSET - 3 * 93 . 1k
The load current can affect the frequency due to its constant on-time control. If constant frequency is a necessity, the PLLIN pin can be used to synchronize the frequency of the LTM4612 to an external clock, as shown in Figures 21 to 23. Input Capacitors LTM4612 is designed to achieve the low input conducted EMI noise due to the fast switching of turn-on and turn-off. In the LTM4612, a high-frequency inductor is integrated into the input line for noise attenuation. VD and VIN pins are available for external input capacitors to form a high frequency filter. As shown in Figure 18, the ceramic capacitor C1 on the VD pins is used to handle most of the RMS current into the converter, so careful attention is needed for capacitor C1 selection. For a buck converter, the switching duty cycle can be estimated as: V D = OUT VIN Without considering the inductor current ripple, the RMS current of the input capacitor can be estimated as: IOUT(MAX ) ICIN(RMS) = * D * ( 1 - D)
CIS25QP
Figure 4. Conducted Emission Scan with 24VIN to 12VOUT at 5A (3 x 10F Ceramic Capacitors on VIN Pads and 1 x 10F Ceramic Capacitor on VD Pads).
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LTM4612 APPLICATIONS INFORMATION
Output Capacitors The LTM4612 is designed for low output voltage ripple. The bulk output capacitors defined as COUT are chosen with low enough effective series resistance (ESR) to meet the output voltage ripple and transient requirements. COUT can be low ESR tantalum capacitor, low ESR polymer capacitor or ceramic capacitor. The typical capacitance is 150F if all ceramic output capacitors are used. Additional output filtering may be required by the system designer, if further reduction of output ripple or dynamic transient spike is required. Table 2 shows a matrix of different output voltages and output capacitors to minimize the voltage droop and overshoot during a 2A/s transient. The table optimizes total equivalent ESR and total bulk capacitance to maximize transient performance. Multiphase operation with multiple LTM4612 devices in parallel will also lower the effective output ripple current due to the phase interleaving operation. Refer to Figure 5 for the normalized output ripple current versus the duty cycle. Figure 5 provides a ratio of peak-to-peak output
1.00 0.95 0.90 0.85 0.80 PEAK-TO-PEAK OUTPUT RIPPLE CURRENT DIr 0.75 0.70 0.65 0.60 0.55 0.50 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 DUTY CYCLE (VO/VIN)
4612 F05
ripple current to the inductor ripple current as functions of duty cycle and the number of paralleled phases. Pick the corresponding duty cycle and the number of phases to get the correct output ripple current value. For example, each phase's inductor ripple current DIr at zero duty cycle is ~4.3A for a 36V to 12V design. The duty cycle is about 0.33. The 2-phase curve has a ratio of ~0.33 for a duty cycle of 0.33. This 0.33 ratio of output ripple current to the inductor ripple current DIr at 4.3A equals 1.4A of the output ripple current (IL). The output voltage ripple has two components that are related to the amount of bulk capacitance and effective series resistance (ESR) of the output bulk capacitance. The equation is: IL + ESR * IL VOUT (P -P) 8 * f * N * COUT Where f is the frequency and N is the number of paralleled phases.
1-PHASE 2-PHASE 3-PHASE 4-PHASE 6-PHASE
RATIO =
Figure 5. Normalized Output Ripple Current vs Duty Cycle, Dlr = VOT/LI
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12
LTM4612 APPLICATIONS INFORMATION
Fault Conditions: Current Limit and Overcurrent Foldback LTM4612 has a current mode controller, which inherently limits the cycle-by-cycle inductor current not only in steady state operation, but also in transient. To further limit current in the event of an overload condition, the LTM4612 provides foldback current limiting. If the output voltage falls by more than 50%, then the maximum output current is progressively lowered to about one sixth of its full current limit value. Soft-Start and Tracking The TRACK/SS pin provides a means to either soft-start the regulator or track it to a different power supply. A capacitor on this pin will program the ramp rate of the output voltage. A 1.5A current source will charge up the external soft-start capacitor to 80% of the 0.6V internal voltage reference minus any margin delta. This will control the ramp of the internal reference and the output voltage. The total soft-start time can be calculated as: C t SOFTSTART 0.8 * 0.6 V - VOUT(MARGIN) * SS 1.5A Output Voltage Tracking Output voltage tracking can be programmed externally using the TRACK/SS pin. The output can be tracked up and down with another regulator. The master regulator's output is divided down with an external resistor divider that is the same as the slave regulator's feedback divider. Figure 6 shows an example of coincident tracking. Ratiometric modes of tracking can be achieved by selecting different resistor values to change the output tracking ratio. The master output must be greater than the slave output for the tracking to work. Figure 7 shows the coincident output tracking. RUN Enable The RUN pin is used to enable the power module. The pin has an internal 5.1V zener to ground. The pin can be driven with 5V logic levels. The RUN pin can also be used as an undervoltage lockout (UVLO) function by connecting a resistor divider from the input supply to the RUN pin. The equation for UVLO threshold: VUVLO = R1+ R2 * 1.5V R2
(
)
If the RUN pin falls below 2.5V, then the soft-start pin is reset to allow for the proper soft-start again. Current foldback and force continuous mode are disabled during the soft-start process. The soft-start function can also be used to control the output ramp rising time, so that another regulator can be easily tracked.
VIN
where R1 is the top resistor, and R2 is the bottom resistor. Power Good The PGOOD pin is an open-drain pin that can be used to monitor valid output voltage regulation. This pin monitors a 10% window around the regulation point, and tracks with margining.
MASTER OUTPUT
100k VD PGOOD RUN CIN MASTER OUTPUT TRACK CONTROL COMP INTVCC R2 100k R1 5.23k DRVCC fSET
10F VIN PLLIN VOUT VFB LTM4612 FCB MARG0 MARG1 MPGM 5.23k PGND
4612 F06 4612 F07
SLAVE OUTPUT COUT
SLAVE OUTPUT OUTPUT VOLTAGE
TRACK/SS SGND
TIME
Figure 6. Coincident Tracking
Figure 7. Coincident Output Tracking
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LTM4612 APPLICATIONS INFORMATION
COMP Pin The pin is the external compensation pin. The module has already been internally compensated for most output voltages. An Excel design tool from Linear Technology will be provided for more control loop optimization. FCB Pin The FCB pin determines whether the bottom MOSFET remains on when current reverses in the inductor. Tying this pin above its 0.6V threshold enables discontinuous operation where the bottom MOSFET turns off when inductor current reverses. FCB pin below the 0.6V threshold forces continuous synchronous operation, allowing current to reverse at light loads and maintaining high frequency operation. PLLIN Pin The power module has a phase-locked loop comprised of an internal voltage controlled oscillator and a phase detector. This allows the internal top MOSFET turn-on to be locked to the rising edge of the external clock. The frequency range is 30% around the set operating frequency. A pulse detection circuit is used to detect a clock on the PLLIN pin to turn on the phase-locked loop. The pulse width of the clock has to be at least 400ns, and 2V in amplitude. During the start-up of the regulator, the phase-locked loop function is disabled. INTVCC and DRVCC Connection An internal low dropout regulator produces an internal 5V supply that powers the control circuitry and DRVCC for driving the internal power MOSFETs. Therefore, if the system does not have a 5V power rail, the LTM4612 can be directly powered by VIN . The gate driver current through the LDO is about 20mA. The internal LDO power dissipation can be calculated as: PLDO_LOSS = 20mA * (VIN - 5V) The LTM4612 also provides the external gate driver voltage pin DRVCC. If there is a 5V rail in the system, it is recommended to connect the DRVCC pin to the external 5V rail. This is especially true for higher input voltages. Do not apply more than 6V to the DRVCC pin. Parallel Operation The LTM4612 device is an inherently current mode controlled device. This allows the paralleled modules to have very good current sharing and balanced thermal on the design. Figure 21 shows a schematic of the parallel design. The voltage feedback equation changes with the variable N as modules are paralleled. The equation: 100k + RFB N VOUT = 0.6 V RFB N is the number of paralleled modules. Radiated EMI Noise High radiated EMI noise is a disadvantage for switching regulators by nature. Fast switching turn-on and turn-off make the large di/dt change in the converters, which act as the radiation sources in most systems. LTM4612 integrates the feature to minimize the radiated EMI noise to meet the most applications with low noise requirements. An optimized gate driver for the MOSFET and a noise cancellation network are installed inside the LTM4612 to achieve the low radiated EMI noise. Figure 8 shows a typical example for the LTM4612 to meet the Class B of CISPR 22 radiated emission limit.
90
EMISSIONS LEVEL (dBV/m)
70
50 CISPR22, CLASS B 30
10
0 0 100 200 300 400 500 600 700 FREQUENCY (MHz) 800 900 1000
4612 F08
Figure 8. Radiated Emission Scan with 24VIN to 12VOUT at 5A Measured in 10 Meter Chamber
Thermal Considerations and Output Current Derating In different applications, LTM4612 operates in a variety of thermal environments. The maximum output current is limited by the environment thermal condition. Sufficient cooling should be provided to help ensure reliable opera4612f
14
LTM4612 APPLICATIONS INFORMATION
tion. When the cooling is limited, proper output current derating is necessary, considering ambient temperature, airflow, input/output condition, and the need for increased reliability. The power loss curves in Figures 9 and 10 can be used in coordination with the load current derating curves in Figures 11 to 16 for calculating an approximate JA for the module. Graph designation delineates between no heat sink, and a BGA heat sink. Each of the load current derating curves will lower the maximum load current as a function of the increased ambient temperature to keep the maximum junction temperature of the power module at
6 5 36VIN TO 15VOUT 4 3 24VIN TO 12VOUT 2 1 0 0 1 2 3 4 5
4612 F09
125C maximum. This will maintain the maximum operating temperature below 125C. Each of the derating curves and the power loss curve that corresponds to the correct output voltage can be used to solve for the approximate JA of the condition. Each figure has three curves that are taken at three different air flow conditions. Each of the derating curves in Figures 11 to 16 can be used with the appropriate power loss curve in either Figure 9 or Figure 10 to derive an approximate JA. Table 3 provides the approximate JA for Figures 11 to 16. A complete explanation of the thermal characteristics is provided in the thermal application note, AN110.
5.0 4.5 200 LFM 0LFM 400LFM
6 5 4 3 2 1 0 0 1 2 3 4 5
4612 F10
4.0 LOAD CURRENT (A) 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 25 35
POWER LOSS (W)
POWER LOSS (W)
36VIN TO 5VOUT
LOAD CURRENT (A)
LOAD CURRENT (A)
45 55 65 75 85 95 AMBIENT TEMPERATURE (C)
105
4612 F11
Figure 9. Power Loss at 12VOUT and 15VOUT
Figure 10. Power Loss at 5VOUT
Figure 11. No Heat Sink with 36VIN to 5VOUT
5.0 4.5 4.0 LOAD CURRENT (A) 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 25 35 45 55 65 75 85 95 AMBIENT TEMPERATURE (C) 105 200 LFM 0LFM 400LFM LOAD CURRENT (A)
5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 25 35 45 55 65 75 85 95 AMBIENT TEMPERATURE (C) 105 200 LFM 0LFM 400LFM LOAD CURRENT (A)
5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 25 35 45 55 65 75 85 95 AMBIENT TEMPERATURE (C) 105 200 LFM 0LFM 400LFM
4612 F12
4612 F13
4612 F14
Figure 12. BGA Heat Sink with 36VIN to 5VOUT
Figure 13. No Heat Sink with 24VIN to 12VOUT
Figure 14. BGA Heat Sink with 24VIN to 12VOUT
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LTM4612 APPLICATIONS INFORMATION
5.0 4.5 4.0 LOAD CURRENT (A) 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 25 35 45 55 65 75 85 AMBIENT TEMPERATURE (C) 95 0LFM 200LFM 400LFM LOAD CURRENT (A) 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 25 35 45 55 65 75 85 AMBIENT TEMPERATURE (C) 95 0LFM 200LFM 400LFM
4612 F15
4612 F16
Figure 15. No Heat Sink with 36VIN to 15VOUT Table 2. Output Voltage Response Versus Component Matrix (Refer to Figure 20)
TYPICAL MEASURED VALUES VENDORS Murata Murata VOUT (V) 5 5 5 5 5 5 10 10 10 10 12 12 15 15 CIN (CERAMIC) 2 x 10F 50V 2 x 10F 50V 2 x 10F 50V 2 x 10F 50V 2 x 10F 50V 2 x 10F 50V 2 x 10F 50V 2 x 10F 50V 2 x 10F 50V 2 x 10F 50V 2 x 10F 50V 2 x 10F 50V 2 x 10F 50V 2 x 10F 50V PART NUMBER GRM32ER61C476KEI5L (47F 16V) , GRM32ER61C226KE20L (22F 16V) , CIN (BULK) 100F 50V 100F 50V 100F 50V 100F 50V 100F 50V 100F 50V 100F 50V 100F 50V 100F 50V 100F 50V 100F 50V 100F 50V 100F 50V 100F 50V COUT1 (CERAMIC) 2 x 22F 16V 4 x 47F 16V 2 x 22F 16V 4 x 47F 16V 2 x 22F 16V 4 x 47F 16V 2 x 22F 16V 4 x 47F 16V 2 x 22F 16V 4 x 47F 16V 2 x 22F 16V 4 x 47F 16V 2 x 22F 16V 4 x 47F 16V COUT2 (BULK) 150F 25V None 150F 25V None 150F 25V None 150F 25V None 150F 25V None 150F 25V None 150F 25V None VIN (V) 12 12 24 24 36 36 24 24 36 36 24 36 28 36 VENDORS Murata TDK
Figure 16. BGA Heat Sink with 36VIN to 15VOUT
PART NUMBER GRM32ER71H106K (10F 50V) , C3225X5RIC226M (22F 16V) , PEAK-TOPEAK (mV) 156 178 166 169 178 172 209 325 197 288 281 375 338 250 RECOVERY TIME (s) 26 14.8 27 14.8 25 15.2 30 35 35 39 37 34.4 70 70 LOAD STEP (A/s) 3 3 3 3 3 3 3 3 3 3 3 3 3 3 RFB (k) 13.7 13.7 13.7 13.7 13.7 13.7 6.34 6.34 6.34 6.34 5.23 5.23 4.12 4.12
DROOP (mV) 86 86 83 86 86 86 111 171 108 153 153 184 178 134
Table 3. 12V and 15V Outputs
DERATING CURVE Figures 11, 13, 15 Figures 11, 13, 15 Figures 11, 13, 15 Figures 12, 14, 16 Figures 12, 14, 16 Figures 12, 14, 16 VIN (V) 24, 36 24, 36 24, 36 24, 36 24, 36 24, 36 POWER LOSS CURVE Figure 9 Figure 9 Figure 9 Figure 9 Figure 9 Figure 9 AIR FLOW (LFM) 0 200 400 0 200 400 HEAT SINK None None None BGA Heat Sink BGA Heat Sink BGA Heat Sink JA (C/W) 13 9.3 8.3 12.2 8.6 7.7
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LTM4612 APPLICATIONS INFORMATION
Table 4. 5V Output
DERATING CURVE Figures 18, 21 Figures 18, 21 Figures 18, 21 Figures 10, 13, 16 Figures 10, 13, 16 Figures 10, 13, 16 VIN (V) 36 36 36 36 36 36 POWER LOSS CURVE Figure 10 Figure 10 Figure 10 Figure 10 Figure 10 Figure 10 AIR FLOW (LFM) 0 200 400 0 200 400 HEAT SINK None None None BGA Heat Sink BGA Heat Sink BGA Heat Sink JA (C/W) 14.9 11.1 10 14 10.4 9.3
Heat Sink Manufacturer
Wakefield Engineering Part No: LTN20069 Phone: 603-635-2800
Safety Considerations The LTM4612 modules do not provide isolation from VIN to VOUT. There is no internal fuse. If required, a slow blow fuse with a rating twice the maximum input current needs to be provided to protect each unit from catastrophic failure. Layout Checklist/Example The high integration of LTM4612 makes the PCB board layout very simple and easy. However, to optimize its electrical and thermal performance, some layout considerations are still necessary. * Use large PCB copper areas for high current path, including VIN, PGND and VOUT. It helps to minimize the PCB conduction loss and thermal stress. * Place high frequency ceramic input and output capacitors next to the VD, PGND and VOUT pins to minimize high frequency noise. * Place a dedicated power ground layer underneath the unit. * Use round corners for the PCB copper layer to minimize the radiated noise. * To minimize the EMI noise and reduce module thermal stress, use multiple vias for interconnection between top layer and other power layers.
* Do not put vias directly on pads. * If vias are placed onto the pads, the the vias must be capped. * Interstitial via placement can also be used if necessary. * Use a separated SGND ground copper area for components connected to signal pins. Connect the SGND to PGND underneath the unit. * Place one or more high frequency ceramic capacitors close to the connection into the system board. Figure 17 gives a good example of the recommended layout.
VIN
CIN
CIN
GND
SIGNAL GND
COUT VOUT
COUT
4612 F17
Figure 17. Recommended PCB Layout
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LTM4612 APPLICATIONS INFORMATION
VOUT VIN 22V TO 36V R5 2M R4 100k R3 100k CLOCK SYNC C1 10F 50V VOUT 12V COUT2 5A 220F 16V
CIN 10F 50V CERAMIC
VD VIN PLLIN VOUT PGOOD RUN LTM4612 ON/OFF VFB COMP INTVCC FCB DRVCC MARG0 fSET MARG1 TRACK/SS MPGM C4 SGND PGND 0.01F
C3 22pF RFB 5.23k MARGIN CONTROL R1 392k 5% MARGIN
4612 F18
COUT1 22F 16V
+
REFER TO TABLE 2
Figure 18. Typical 22V to 36VIN, 12V at 5A Design
VOUT VIN 5V TO 36V CLOCK SYNC C1 10F 50V VOUT 3.3V 5A
R4 100k CIN 10F 50V CERAMIC
R3 100k
VD VIN PLLIN VOUT PGOOD RUN ON/OFF VFB COMP LTM4612 INTVCC FCB DRVCC
C3 22pF RFB 22.1k
COUT1 22F 6.3V
+
COUT2 220F 6.3V
EXTERNAL 5V SUPPLY IMPROVES EFFICIENCY-- ESPECIALLY FOR HIGH INPUT VOLTAGES
RfSET 191k 1% C4 0.01F
fSET TRACK/SS SGND
MARG0 MARG1 MPGM PGND
MARGIN CONTROL R1 392k 5% MARGIN
4612 F19
REFER TO TABLE 2
Figure 19. Typical 5V to 36VIN, 3.3V at 5A Design with 400kHz Frequency
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LTM4612 APPLICATIONS INFORMATION
VOUT VIN 26V TO 36V R4 100k R3 100k CLOCK SYNC C1 10F 50V VOUT 15V 4A
RfSET 806k, 1%
CIN 10F 50V CERAMIC
VD VIN PLLIN VOUT PGOOD RUN LTM4612 ON/OFF VFB COMP INTVCC FCB DRVCC MARG0 fSET MARG1 TRACK/SS MPGM SGND PGND C4 0.01F
C3 22pF RFB 4.12k MARGIN CONTROL R1 392k 5% MARGIN
4612 F20
COUT1 22F 16V
+
COUT2 220F 16V
Figure 20. 26V to 36VIN, 15V at 4A Design with Reduced Frequency
VIN 20V TO 36V
VOUT C1 10F 50V
R4 100k
R2 100k
CLOCK SYNC 0 PHASE VOUT 12V, 10A C6 47pF C3 22F 16V
C2 10F 50V
+
2-PHASE OSCILLATOR R5 124k C11 0.1F V+ OUT1 GND OUT2 SET MOD LTC6908-1
C5 100F 50V
VD VIN PLLIN PGOOD VOUT RUN LTM4612 VFB COMP FCB INTVCC DRVCC MARG0 fSET MARG1 TRACK/SS MPGM C7 SGND PGND 0.33F
+
C4 220F 16V
MARGIN CONTROL R1 392k RFB 2.61k VOUT = 0.6V * 100k/N + RFB RFB
5% MARGIN
C11 10F 50V
CLOCK SYNC 180 PHASE
C8 10F 50V
VD VIN PLLIN VOUT PGOOD RUN LTM4612 VFB COMP FCB INTVCC DRVCC fSET TRACK/SS SGND MARG0 MARG1 MPGM PGND
4612 F21
C9 22F 16V
+
C10 220F 16V
R6 392k
Figure 21. 2-Phase, Parallel 12V at 10A Design
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19
LTM4612 APPLICATIONS INFORMATION
12V VIN 22V TO 36V C1 10F 50V VD VIN CLOCK SYNC 0 PHASE PLLIN C6 22pF C3 22F 16V 12V AT 5A
R4 100k
R2 100k
+
C5 100F 50V
C2 10F 50V C7 0.15F
PGOOD VOUT RUN LTM4612 VFB COMP FCB INTVCC DRVCC MARG0 fSET MARG1 TRACK/SS MPGM SGND PGND 5% MARGIN
+
C4 220F 16V
MARGIN CONTROL R1 392k RFB1 5.23k
2-PHASE OSCILLATOR V+ R5 118k C11 0.1F OUT1 GND OUT2 SET MOD LTC6908-1 R3 100k R7 100k 10V
C11 10F 50V
CLOCK SYNC 180 PHASE 10V AT 5A C1 22pF C9 22F 16V
VD VIN PLLIN VOUT PGOOD RUN LTM4612 COMP INTVCC DRVCC fSET TRACK/SS SGND VFB FCB MARG0 MARG1 MPGM PGND MARGIN CONTROL R6 392k
4612 F22
+
C10 220F 16V
12V TRACK C8 10F 50V R8 100k R9 6.24k
RFB2 6.24k
Figure 22. 2-Phase, 12V and 10V at 5A Design
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20
LTM4612 APPLICATIONS INFORMATION
VIN 7V TO 36V 5V C1 10F 50V R4 100k R2 100k
CLOCK SYNC 0 PHASE 5V AT 5A C6 22pF C3 22F 6.3V
C2 10F 50V
+
C5 100F 50V
RfSET1 150k
C7 0.15F
VD VIN PLLIN VOUT PGOOD RUN LTM4612 VFB COMP INTVCC FCB DRVCC MARG0 fSET MARG1 TRACK/SS MPGM SGND PGND 5% MARGIN
+
C4 220F 6.3V
MARGIN CONTROL R1 392k RFB1 13.7k
2-PHASE OSCILLATOR R5 200k C11 0.1F V+ OUT1 GND OUT2 SET MOD LTC6908-1 R3 100k R7 100k 3.3V
5V TRACK C8 10F 50V R8 100k R9 22.1k RfSET2 100k
C11 CLOCK SYNC 10F 180 PHASE 50V VIN VD PLLIN VOUT PGOOD RUN VFB COMP LTM4612 FCB INTVCC DRVCC fSET TRACK/SS SGND MARG0 MARG1 MPGM PGND
3.3V AT 5A C1 22pF C9 22F 6.3V
+
C10 220F 6.3V
MARGIN CONTROL R6 392k
4612 F23
RFB2 22.1k
Figure 23. 2-Phase, 5V and 3.3V at 5A Design with 500kHz Frequency
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21
LTM4612 PACKAGE DESCRIPTION
Pin Assignment Tables (Arranged by Pin Function)
PIN NAME A1 A2 A3 A4 A5 A6 B1 B2 B3 B4 B5 B6 C1 C2 C3 C4 C5 C6 VIN VIN VIN VIN VIN VIN VIN VIN VIN VIN VIN VIN VIN VIN VIN VIN VIN VIN D1 D2 D3 D4 D5 D6 E1 E2 E3 E4 E5 E6 E7 E8 F1 F2 F3 F4 F5 F6 F7 F8 F9 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 PIN NAME PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 PIN NAME VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT A7 A8 A9 A10 A11 A12 B7 B8 B9 B10 B11 B12 C7 C8 C9 C10 C11 C12 D7 D8 D9 D10 D11 D12 E9 E10 E11 E12 F10 F11 F12 G12 H12 J12 K12 L12 M12 PIN NAME INTVCC PLLIN TRACK/SS RUN COMP MPGM VD RUN MPGM fSET VD DRVCC MARG1 MARG0 SGND COMP MARG1 DRVCC DRVCC VFB PGOOD SGND NC NC NC FCB
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LGA Package 133-Lead (15mm x 15mm x 2.82mm)
(Reference LTM DWG # 05-08-1766 Rev O)
DETAIL A X Y 12 11 10 9 8 15 BSC MOLD CAP SUBSTRATE 13.97 BSC 7 6 5 4 3 2 1 PADS SEE NOTES M 3 DETAIL B 1.9050 3.1750 4.4450 5.7150 6.9850 0.630 0.025 SQ. 133x eee S X Y L K J H G F E D C B A C(0.30) PAD 1 2.72 - 2.92 0.12 - 0.28 13.97 BSC
PACKAGE DESCRIPTION
aaa Z
15 BSC
0.27 - 0.37 2.45 - 2.55 DETAIL B bbb Z Z
PAD 1 CORNER
1.27 BSC
4
aaa Z
PACKAGE TOP VIEW
PACKAGE BOTTOM VIEW
6.9850
5.7150
4.4450
3.1750
1.9050
6.9850
5.7150
4.4450 DETAIL A
3.1750
1.9050
0.6350 0.0000 0.6350
NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 2. ALL DIMENSIONS ARE IN MILLIMETERS 3 4 LAND DESIGNATION PER JESD MO-222, SPP-010
LTMXXXXXX Module
COMPONENT PIN "A1"
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
DETAILS OF PAD #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE PAD #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE 5. PRIMARY DATUM -Z- IS SEATING PLANE 6. THE TOTAL NUMBER OF PADS: 133 SYMBOL TOLERANCE aaa 0.10 0.10 bbb 0.05 eee
TRAY PIN 1 BEVEL
0.6350 0.0000 0.6350
1.9050
3.1750
4.4450
5.7150
6.9850
PACKAGE IN TRAY LOADING ORIENTATION
LGA 133 1107 REV O
SUGGESTED PCB LAYOUT TOP VIEW
LTM4612
23
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LTM4612 PACKAGE PHOTOGRAPH
15mm 2.8mm
15mm
4612 F24
RELATED PARTS
PART NUMBER LTC2900 LTM4600 LTM4600HVMP LTM4601/ LTM4601A LTM4602 LTM4603 LTM4604A LTM4606 LTM4608A LTM8020 LTM8021 DESCRIPTION Quad Supply Monitor with Adjustable Reset Timer 10A DC/DC Module Military Plastic 10A DC/DC Module 12A DC/DC Module with PLL, Output Tracking/ Margining and Remote Sensing 6A DC/DC Module 6A DC/DC Module with PLL and Output Tracking/ Margining and Remote Sensing Low VIN 4A DC/DC Module Ultralow Noise 6A, DC/DC Module Low VIN 8A DC/DC Module High VIN 0.2A DC/DC Step-Down Module High VIN 0.5A DC/DC Step-Down Module COMMENTS Monitors Four Supplies; Adjustable Reset Timer Basic 10A DC/DC Module, LGA Package Guaranteed Operation from -55C to 125C Ambient, LGA Package Synchronizable, PolyPhase Operation, LTM4601-1/LTM4601A-1 Version Has No Remote Sensing, LGA Package Pin Compatible with the LTM4600, LGA Package Synchronizable, PolyPhase Operation, LTM4603-1 Version Has No Remote Sensing, Pin Compatible with the LTM4601, LGA Package 2.375V VIN 5.5V, 0.8V VOUT 5V, 9mm x 15mm x 2.3mm LGA Package Ultralow Noise, with PLL, Output Tracking and Margining, LTM4612 Pin Compatible 2.4V VIN 5.5V; 0.6V VOUT 5V; 9mm x 15mm x 2.8mm LGA Package 4V VIN 36V, 1.25V VOUT 5V 6.25mm x 6.25mm x 2.3mm LGA Package 3V VIN 36V, 0.8V VOUT 5V 6.25mm x 11.25mm x 2.8mm LGA Package Pin Compatible; 4.5V VIN 36V; 9mm x 11.25mm x 2.8mm LGA Package
LTM8022/LTM8023 36VIN, 1A and 2A DC/DC Module
4612f
24 Linear Technology Corporation
(408) 432-1900 FAX: (408) 434-0507
LT 0808 * PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
www.linear.com
(c) LINEAR TECHNOLOGY CORPORATION 2008

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